dc.contributor.author | Mirosanlou, Reza | |
dc.contributor.author | Hassan, Mohamed | |
dc.contributor.author | Pellizzoni, Rodolfo | |
dc.date.accessioned | 2020-03-02 17:24:55 (GMT) | |
dc.date.available | 2020-03-02 17:24:55 (GMT) | |
dc.date.issued | 2020-03-02 | |
dc.identifier.uri | http://hdl.handle.net/10012/15678 | |
dc.description | This document provides the appendix to: Reza Mirosanlou, Mohamed Hassan and Rodolfo Pellizzoni, DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining. Proceedings of the 26th IEEE Real-Time and Embedded Technology and Applications Symposium, Sydney, Australia, April 2020. | en |
dc.description.abstract | Worst-case execution bounds for real-time programs are highly impacted by the latency of accessing hardware shared resources, such as off-chip DRAM. While many different memory controller designs have been proposed in the literature, there is a trade-off between average-case performance and predictable worst-case bounds, as techniques targeted at improving the former can harm the latter and vice-versa. We find that taking advantage of pipelining between different commands can improve both, but incorporating pipelining effects in worst-case analysis is challenging. In this work, we introduce a novel DRAM controller that successfully balances performance and predictability by employing a dynamic pipelining scheme. We show that the schedule of DRAM commands is akin to a two-stage two-mode pipeline, and hence, design an easily-implementable admission rule that allows us to dynamically add requests to the pipeline without hurting worst-case bounds. | en |
dc.language.iso | en | en |
dc.subject | Real-time systems, Memory Architecture, DRAM | en |
dc.title | APPENDIX to DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining | en |
dc.type | Technical Report | en |
uws.contributor.affiliation1 | Faculty of Engineering | en |
uws.contributor.affiliation2 | Electrical and Computer Engineering | en |
uws.typeOfResource | Text | en |
uws.peerReviewStatus | Reviewed | en |
uws.scholarLevel | Graduate | en |