Fundamental Physics and Optimization of Gate-All-Around Stacked Nanosheet FETs Without Gate Metal Interlayers

Abstract

Stacked Nanosheet Field-Effect Transistors (SNS-FET) are a state-of-the-art design which have allowed for scaling of transistors down to sub 5 nm scales. The gate-all-around (GAA) architecture, paired with the thin and wide nanosheet channel, allows for excellent gate control resulting in reduced short channel effects. With the removal of the interlayer gate metal in the GAA-FET architecture a design with simpler fabrication procedures can be created. There have been studies that have demonstrated this design’s electrical performance, the design remains relatively underexplored, and this thesis seeks to study the underlying physics and the optimization potential of this metal-interlayer-free (MI-free) GAA-FET architecture. This thesis presents two computational modeling studies based on the self-consistent solution to the Poisson and Schrodinger equation within the nonequilibrium Green’s function (NEGF) utilizing a tight-binding Hamiltonian. The studies aim to (i) thoroughly understand the fundamental physics of the MI-free design and (ii) propose optimization strategies to maximize the potential of the device. The first study presents the study of the underlying physics and the potential optimization of the MI-free GAA-FET architecture. The study uses graphene nanoribbon (GNR) as the channel material due to its simple tight-binding Hamiltonian matrix which significantly reduces computational resources. In this study various device design optimization have been studied. This study aims to understand the impact of the removal of the interlayer gate metal and how this interlayer oxide thickness impact device performance. This study looks to understand the importance and the role the interlayer gate metal and the oxide thickness plays on the overall device performance. It was discovered that with optimizing the interlayer spacing the subthreshold swing (SS) and ON/OFF current ratio (ION/IOFF) could be improved. With proper optimization the 3-ribbon device showed a 47% improvement in ION/IOFF compared to the 1-ribbon device. The study also saw that lateral oxide thickness played a greater role in device performance for the MI-free GAA-FETs as ION/IOFF and SS for the 3-ribbon device can be improved by 186% and 27% as the lateral oxides thicknesses are varied from 4nm to 1nm. With proper optimization it was discovered that short channel effects can be suppressed, and device-to-device variability can be significantly reduced for the MI-free devices. The second study aims to understand the performance of the MI-free FET device in a double gate design. In this modeling study, a 2D model with monolayer black phosphorous channel was utilized to explore the potential of the device when the nanosheets are far wider thus effectively removing the influence of the side gates. In this study it was discovered that without the gate control provided by the side gates, it was better to reduce interlayer spacing to improve the coupling to the top/bottom gates. The dielectric materials for the interlayer region were explored to understand the ideal optimization strategies for oxide materials. It was shown that using a lower dielectric constant would result in slightly improved performance due to the reduced screening effect. Overall, this study demonstrated the importance of the side gates and proper interlayer permittivity optimization.