Design of a Multi-Stage Power Amplifier for a 16 Element MIMO Transmitter Testbed

Abstract

The next-generation standard for fifth-generation (5G) wireless communication demands significant advancements in the transmitter front end compared to its predecessor. This need arises from the exponential increase in both data rate requirements and the number of connected devices. The primary approach to achieving these improvements relies on the adoption of massive multiple-input multiple-output (mMIMO) systems. These systems, combined with beamforming technology, which enhances the equivalent isotropic radiated power (EIRP) by focusing transmission power in specific directions, increase the data rate of the communication systems.

While 5G aims to leverage millimeter-wave frequencies for increased bandwidth and data rates, the sub-6 GHz spectrum remains valuable, offering a practical balance between range and performance. Given the new performance requirements, the power amplifier (PA) must exhibit high linearity to minimize memory effects and distortion. As the most power-intensive component in the transmitter chain, the PA also faces increasing efficiency challenges, particularly due to the rising peak-to-average power ratio (PAPR) in 5G systems. In mMIMO configurations, additional complexities arise from factors such as load mismatch and antenna crosstalk, which further impact PA performance. Just as important, electromagnetic interference (EMI) within the transmission chain itself can degrade overall system efficiency —an often overlooked concern, which is the issue that this thesis addresses.

To address these challenges, this thesis presents a multi-stage Class AB PA operating in the 3.2–3.8 GHz range, designed for linearization within a 4×4 mMIMO transmitter array. External aluminum shielding is also employed to counteract the EMI. The PA is evaluated through S-parameter, continuous-wave (CW), and modulated signal simulations. CW simulations indicate that the driver and PA together achieve a small-signal gain of approximately 23–25 dB. The PA, utilizing 6W MACOM CGHV1F006 transistors, reaches saturation at 37 dBm output power. The 1 dB compression point is observed around 36 dBm, providing a broad linearity range before saturation.

The PA-stage demonstrates power-added efficiency (PAE) between 54% and 61% at maximum power, with a maximum phase distortion of -4 degrees at high-power levels. Modulated signal simulations, conducted with a 100 MHz modulation bandwidth, confirm that the PA is linearizable under single-input single-output (SISO) digital predistortion (DPD). The application of DPD reduces the adjacent channel power ratio (ACPR) from -35 dBc to -55 dBc, demonstrating a significant improvement in linearity compared to the non-DPD case.