The design and analysis of asynchronous up-down counters

Abstract

The goal of this report is to investigate up-down counter implementations in the framework of delay-insensitive circuits. An up-down counter is a counter on which two operations can be performed: an increment by one and a decrement by one. For N larger than zero, an up-down N-counter counts in the range from zero through N. In the counters we design, the value of the counter, or its count, cannot be read, but it is possible to detect whether the counter's value is zero, N, or somewhere in between. Up-down counters have many applications. For example, they can be useful in implementing queues or stacks.

Various implementations for up-down N-counters are presented for any N larger than zero. All counter designs are analyzed with respect to three performance criteria, namely area complexity, response time, and power consumption. One of the designs is optimal with respect to all three performance criteria. Its area complexity grows logarithmically with N, and its response time and power consumption are independent of N.